The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC design and material have produced generations of ICs where each generation has smaller and more complex circuits than previous generations. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, high-k (HK) dielectric material and metal are adopted to form a gate stack. Although existing methods of fabricating IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, challenges rise to develop robust processes for increasing dielectric constant of a HK gate dielectric layer.